Parametric results for: SN74LVC00APWR under Gates

All Filters Family JESD-30 Code JESD-609 Code Length Load Capacitance (CL) Logic IC Type Manufacturer Max I(ol) Moisture Sensitivity Level Number of Functions Number of Inputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Package Body Material Package Code Package Equivalence Code Package Shape Package Style Prop. Delay@Nom-Sup Propagation Delay (tpd) Schmitt Trigger Supply Voltage-Nom (Vsup) Surface Mount Family (1)

LVC/LCX/Z 4

4 hits Apply

R-PDSO-G14 4

4 hits Apply

e4 3

4 hits Apply

5 mm 4

4 hits Apply

Load Capacitance (CL) (1)

50 pF 4

4 hits Apply

NAND GATE 4

4 hits Apply

Manufacturer (1)

Texas Instruments 4

4 hits Apply

24 mA 4

4 hits Apply

1 3

4 hits Apply

Number of Functions (1)

4.0 4

4 hits Apply

Number of Inputs (1)

2 4

4 hits Apply

14 4

4 hits Apply

125.0 °C 4

4 hits Apply

-40.0 °C 4

4 hits Apply

PLASTIC/EPOXY 4

4 hits Apply

Package Code (1)

TSSOP 4

4 hits Apply

TSSOP14,.25 4

4 hits Apply

RECTANGULAR 4

4 hits Apply

SMALL OUTLINE, THIN PROFILE, SHRINK PITCH 4

4 hits Apply

Prop. Delay@Nom-Sup (1)

5.5 ns 4

4 hits Apply

Propagation Delay (tpd) (1)

14 ns 4

4 hits Apply

Schmitt Trigger (1)

NO 4

4 hits Apply

Supply Voltage-Nom (Vsup) (1)

3.3 V 4

4 hits Apply

Surface Mount (1)

YES 4

4 hits Apply