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Field Programmable Gate Array, 56 CLBs, 15000 Gates, 1000MHz, 15200-Cell, CMOS, PBGA900, 31 X 31 MM, LEAD FREE, FPBGA-900
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
LFSCM3GA15EP1-5FN900I by Lattice Semiconductor Corporation is a Field Programmable Gate Array.
Field Programmable Gate Arrays are under the broader part category of Programmable Logic Devices.
Programmable Logic Devices (PLDs) are reconfigurable digital components that can be customized for different applications, offering flexibility and improved performance over fixed logic devices. Read more about Programmable Logic Devices on our Programmable Logic part category page.
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LFSCM3GA15EP1-5FN900I
Lattice Semiconductor Corporation
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Datasheet
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LFSCM3GA15EP1-5FN900I
Lattice Semiconductor Corporation
Field Programmable Gate Array, 56 CLBs, 15000 Gates, 1000MHz, 15200-Cell, CMOS, PBGA900, 31 X 31 MM, LEAD FREE, FPBGA-900
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Pbfree Code | Yes | |
Rohs Code | Yes | |
Part Life Cycle Code | Obsolete | |
Ihs Manufacturer | LATTICE SEMICONDUCTOR CORP | |
Part Package Code | BGA | |
Package Description | 31 X 31 MM, LEAD FREE, FPBGA-900 | |
Pin Count | 900 | |
Reach Compliance Code | compliant | |
ECCN Code | 3A991.D | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Lattice Semiconductor | |
Clock Frequency-Max | 139.8 MHz | |
Combinatorial Delay of a CLB-Max | 0.192 ns | |
JESD-30 Code | S-PBGA-B900 | |
JESD-609 Code | e1 | |
Length | 31 mm | |
Moisture Sensitivity Level | 3 | |
Number of CLBs | 56 | |
Number of Equivalent Gates | 15000 | |
Number of Inputs | 300 | |
Number of Logic Cells | 15200 | |
Number of Outputs | 300 | |
Number of Terminals | 900 | |
Operating Temperature-Max | 85 °C | |
Operating Temperature-Min | -40 °C | |
Organization | 56 CLBS, 15000 GATES | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | BGA | |
Package Equivalence Code | BGA900,30X30,40 | |
Package Shape | SQUARE | |
Package Style | GRID ARRAY | |
Peak Reflow Temperature (Cel) | 250 | |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
Qualification Status | Not Qualified | |
Seated Height-Max | 2.6 mm | |
Supply Voltage-Max | 1.26 V | |
Supply Voltage-Min | 0.95 V | |
Supply Voltage-Nom | 1.2 V | |
Surface Mount | YES | |
Technology | CMOS | |
Temperature Grade | INDUSTRIAL | |
Terminal Finish | Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5) | |
Terminal Form | BALL | |
Terminal Pitch | 1 mm | |
Terminal Position | BOTTOM | |
Time@Peak Reflow Temperature-Max (s) | 40 | |
Width | 31 mm |
This table gives cross-reference parts and alternative options found for LFSCM3GA15EP1-5FN900I. The Form Fit Function (FFF) tab will give you the options that are more likely to serve as direct pin-to-pin alternates or drop-in parts. The Functional Equivalents tab will give you options that are likely to match the same function of LFSCM3GA15EP1-5FN900I, but it may not fit your design. Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.
Part Number | Manufacturer | Composite Price | Description | Compare |
---|---|---|---|---|
LFSCM3GA15EP1-5F900C | Lattice Semiconductor Corporation | Check for Price | Field Programmable Gate Array, 56 CLBs, 15000 Gates, 1000MHz, 15200-Cell, CMOS, PBGA900, 31 X 31 MM, FPBGA-900 | LFSCM3GA15EP1-5FN900I vs LFSCM3GA15EP1-5F900C |
Lattice provides a PCB Design and Layout Guide (UG057) that offers guidelines for PCB layout, routing, and signal integrity. It's recommended to follow these guidelines to ensure optimal performance and signal quality.
Lattice recommends using an external POR circuit with a voltage supervisor IC, such as the TLV7031, to ensure a reliable power-on reset. The datasheet provides a reference design for this circuit.
The LFSCM3GA15EP1-5FN900I has a thermal design power (TDP) of 1.5W. To manage thermal performance, Lattice recommends using a heat sink, thermal interface material, and following the thermal management guidelines in the datasheet.
Lattice provides a Clocking and PLL User Guide (UG055) that explains how to configure the FPGA's clocking and PLLs using the Lattice Diamond software. The guide covers clock domain crossing, PLL configuration, and clock tree synthesis.
The LFSCM3GA15EP1-5FN900I has built-in security features such as AES encryption, secure boot, and bitstream encryption. Lattice recommends following the Security User Guide (UG056) to implement these features and ensure secure device operation.