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Consumer Circuit, CMOS, PBGA49, 3.60 X 3.90 MM, 0.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-211C, WCSP-49
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
55AC4801
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Newark | Cirwm8962Becsn/R Rohs Compliant: Yes |Cirrus Logic WM8962BECSN/R RoHS: Compliant Min Qty: 5000 Package Multiple: 1 Date Code: 0 Container: Reel | 0 |
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Buy Now | |
DISTI #
WM8962BECSN/RCT-ND
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DigiKey | IC CODEC STEREO LP 49WLCSP Min Qty: 1 Lead time: 23 Weeks Container: Cut Tape (CT), Digi-Reel®, Tape & Reel (TR) |
9942 In Stock |
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$5.4625 / $11.4000 | Buy Now |
DISTI #
WM8962BECSN/R
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Avnet Americas | Stereo Codec, 1.7 V to 2 V, 49 Pins, WLCSP - Tape and Reel (Alt: WM8962BECSN/R) RoHS: Compliant Min Qty: 5000 Package Multiple: 5000 Lead time: 23 Weeks, 0 Days Container: Reel | 0 |
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$4.8070 / $5.1566 | Buy Now |
DISTI #
WM8962BECSN/R
|
Avnet Americas | Stereo Codec, 1.7 V to 2 V, 49 Pins, WLCSP - Tape and Reel (Alt: WM8962BECSN/R) RoHS: Compliant Min Qty: 5000 Package Multiple: 5000 Lead time: 23 Weeks, 0 Days Container: Reel | 0 |
|
$4.8070 / $5.1566 | Buy Now |
DISTI #
238-WM8962BECSN/R
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Mouser Electronics | Interface - CODECs Stereo CODEC with Audio Enhancement RoHS: Compliant | 6829 |
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$5.3400 / $11.4000 | Buy Now |
DISTI #
WM8962BECSN/R
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Avnet Silica | Stereo Codec 17 V to 2 V 49 Pins WLCSP (Alt: WM8962BECSN/R) RoHS: Compliant Min Qty: 5000 Package Multiple: 5000 Lead time: 25 Weeks, 0 Days | Silica - 0 |
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Buy Now | |
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LCSC | Codec 8kHz96kHz CSP-49(3.6x3.9) Audio Interface ICs ROHS | 35 |
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$4.2727 / $5.9337 | Buy Now |
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Win Source Electronics | IC CODEC STEREO LP 49WLCSP | 5581 |
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$5.4239 / $7.0062 | Buy Now |
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WM8962BECSN/R
Cirrus Logic
Buy Now
Datasheet
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Compare Parts:
WM8962BECSN/R
Cirrus Logic
Consumer Circuit, CMOS, PBGA49, 3.60 X 3.90 MM, 0.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-211C, WCSP-49
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Rohs Code | Yes | |
Part Life Cycle Code | Active | |
Ihs Manufacturer | CIRRUS LOGIC INC | |
Package Description | 3.60 X 3.90 MM, 0.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-211C, WCSP-49 | |
Reach Compliance Code | compliant | |
HTS Code | 8542.39.00.01 | |
Factory Lead Time | 23 Weeks | |
Samacsys Manufacturer | Cirrus Logic | |
Consumer IC Type | CONSUMER CIRCUIT | |
JESD-30 Code | R-PBGA-B49 | |
Length | 3.984 mm | |
Number of Functions | 1 | |
Number of Terminals | 49 | |
Operating Temperature-Max | 85 °C | |
Operating Temperature-Min | -40 °C | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | VFBGA | |
Package Equivalence Code | BGA49,7X7,20 | |
Package Shape | RECTANGULAR | |
Package Style | GRID ARRAY, VERY THIN PROFILE, FINE PITCH | |
Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
Qualification Status | Not Qualified | |
Seated Height-Max | 0.75 mm | |
Supply Current-Max | ||
Supply Voltage-Max (Vsup) | 2 V | |
Supply Voltage-Min (Vsup) | 1.62 V | |
Surface Mount | YES | |
Technology | CMOS | |
Temperature Grade | INDUSTRIAL | |
Terminal Form | BALL | |
Terminal Pitch | 0.5 mm | |
Terminal Position | BOTTOM | |
Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | |
Width | 3.594 mm |
The recommended power-up sequence is to apply VDD first, followed by VDDIO, and then the clock signal. This ensures that the internal voltage regulators are powered up correctly.
The WM8962 can be configured using the I2C interface. The device has several registers that control the audio settings, such as gain, mute, and routing. Refer to the datasheet for the register map and configuration details.
The maximum input signal level that the WM8962 can handle is 2.2Vrms. Exceeding this level may result in distortion or damage to the device.
To optimize the WM8962 for low power consumption, use the power-down modes, reduce the clock frequency, and adjust the voltage regulators. Additionally, use the dynamic biasing feature to reduce power consumption during idle periods.
The recommended layout and routing for the WM8962 involves keeping the analog and digital signals separate, using a solid ground plane, and minimizing the length of the clock signal traces. Refer to the datasheet for more detailed layout and routing guidelines.