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Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-SOIC 0 to 70
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
SN74LS76ADR by Texas Instruments is an FF/Latch.
FF/Latches are under the broader part category of Logic Components.
Digital logic governs the behavior of signals in electronic circuits, enabling complex decisions based on simple binary inputs (yes/no). Logic components perform operations from these signals. Read more about Logic Components on our Logic part category page.
Part # | Distributor | Description | Stock | Price | Buy | |
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Vyrian | Peripheral ICs | 824 |
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RFQ |
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SN74LS76ADR
Texas Instruments
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SN74LS76ADR
Texas Instruments
Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-SOIC 0 to 70
|
Pbfree Code | No | |
Rohs Code | No | |
Part Life Cycle Code | Obsolete | |
Ihs Manufacturer | TEXAS INSTRUMENTS INC | |
Part Package Code | SOIC | |
Package Description | SOP, SOP16,.25 | |
Pin Count | 16 | |
Reach Compliance Code | not_compliant | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Texas Instruments | |
Additional Feature | MASTER SLAVE OPERATION | |
Family | LS | |
JESD-30 Code | R-PDSO-G16 | |
Length | 9.9 mm | |
Load Capacitance (CL) | 15 pF | |
Logic IC Type | J-K FLIP-FLOP | |
Number of Bits | 2 | |
Number of Functions | 2 | |
Number of Terminals | 16 | |
Operating Temperature-Max | 70 °C | |
Operating Temperature-Min | ||
Output Polarity | COMPLEMENTARY | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | SOP | |
Package Equivalence Code | SOP16,.25 | |
Package Shape | RECTANGULAR | |
Package Style | SMALL OUTLINE | |
Packing Method | TR | |
Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
Power Supply Current-Max (ICC) | 6 mA | |
Propagation Delay (tpd) | 20 ns | |
Qualification Status | Not Qualified | |
Seated Height-Max | 1.75 mm | |
Supply Voltage-Max (Vsup) | 5.25 V | |
Supply Voltage-Min (Vsup) | 4.75 V | |
Supply Voltage-Nom (Vsup) | 5 V | |
Surface Mount | YES | |
Technology | TTL | |
Temperature Grade | COMMERCIAL | |
Terminal Form | GULL WING | |
Terminal Pitch | 1.27 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | |
Trigger Type | NEGATIVE EDGE | |
Width | 3.9 mm | |
fmax-Min | 45 MHz |
This table gives cross-reference parts and alternative options found for SN74LS76ADR. The Form Fit Function (FFF) tab will give you the options that are more likely to serve as direct pin-to-pin alternates or drop-in parts. The Functional Equivalents tab will give you options that are likely to match the same function of SN74LS76ADR, but it may not fit your design. Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.
Part Number | Manufacturer | Composite Price | Description | Compare |
---|---|---|---|---|
DM74LS112AMX | Fairchild Semiconductor Corporation | Check for Price | J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO16, 0.150 INCH, PLASTIC, SOP-16 | SN74LS76ADR vs DM74LS112AMX |
DM74LS112AMX | Rochester Electronics LLC | Check for Price | J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO16, 0.150 INCH, PLASTIC, SOP-16 | SN74LS76ADR vs DM74LS112AMX |
SN74LS76ADR2 | onsemi | Check for Price | LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOIC-16 | SN74LS76ADR vs SN74LS76ADR2 |
HD74LS112RP | Renesas Electronics Corporation | Check for Price | LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, FP-16DN | SN74LS76ADR vs HD74LS112RP |
SN74LS112ADR | Texas Instruments | Check for Price | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 | SN74LS76ADR vs SN74LS112ADR |
SN74LS112AD | Motorola Mobility LLC | Check for Price | LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOIC-16 | SN74LS76ADR vs SN74LS112AD |
SN74LS112ADG4 | Texas Instruments | Check for Price | LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GREEN, PLASTIC, SOIC-16 | SN74LS76ADR vs SN74LS112ADG4 |
SN74LS76AD | Texas Instruments | Check for Price | Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-SOIC 0 to 70 | SN74LS76ADR vs SN74LS76AD |
HD74LS76ARPEL | Renesas Electronics Corporation | Check for Price | LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 3.95 X 9.90 MM, 1.27 MM PITCH, PLASTIC, SOP-16 | SN74LS76ADR vs HD74LS76ARPEL |
The maximum clock frequency of the SN74LS76ADR is 25 MHz.
The SN74LS76ADR requires a single 5V power supply, and it's recommended to use a decoupling capacitor of 0.1uF to 1uF between VCC and GND to ensure proper power supply decoupling.
The SN74LS76ADR can sink or source up to 24mA of current per output pin.
The CLR input should be tied to VCC through a pull-up resistor (e.g., 1kΩ) to ensure that the flip-flops are properly reset. A low-going pulse on CLR will reset the flip-flops.
The typical propagation delay of the SN74LS76ADR is 10ns to 15ns, depending on the operating conditions and load capacitance.