Part Details for PCM1702U by Texas Instruments
Results Overview of PCM1702U by Texas Instruments
- Distributor Offerings: (0 listings)
- Number of FFF Equivalents: (1 replacement)
- CAD Models: (Request Part)
- Number of Functional Equivalents: (10 options)
- Part Data Attributes: (Available)
- Reference Designs: (Not Available)
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
PCM1702U Information
PCM1702U by Texas Instruments is a Digital to Analog Converter.
Digital to Analog Converters are under the broader part category of Converters.
A converter is an electrical circuit that transforms electric energy into a different form that will support a elecrical load needed by a device. Read more about Converters on our Converters part category page.
Part Details for PCM1702U
PCM1702U CAD Models
PCM1702U Part Data Attributes
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PCM1702U
Texas Instruments
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PCM1702U
Texas Instruments
120dB SNR Stereo DAC with BiCMOS Advanced Sign Magnitude Architecture 20-SO
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Pbfree Code | No | |
Rohs Code | Yes | |
Part Life Cycle Code | Obsolete | |
Ihs Manufacturer | TEXAS INSTRUMENTS INC | |
Part Package Code | SOIC | |
Package Description | ROHS COMPLIANT, PLASTIC, SOP-20 | |
Pin Count | 20 | |
Reach Compliance Code | unknown | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Texas Instruments | |
Converter Type | D/A CONVERTER | |
Input Bit Code | 2'S COMPLEMENT BINARY | |
Input Format | SERIAL | |
JESD-30 Code | R-PDSO-G20 | |
Length | 12.6 mm | |
Moisture Sensitivity Level | 2 | |
Negative Supply Voltage-Nom | -5 V | |
Number of Bits | 20 | |
Number of Functions | 1 | |
Number of Terminals | 20 | |
Operating Temperature-Max | 85 °C | |
Operating Temperature-Min | -25 °C | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | SOP | |
Package Equivalence Code | SOP20,.3 | |
Package Shape | RECTANGULAR | |
Package Style | SMALL OUTLINE | |
Peak Reflow Temperature (Cel) | 260 | |
Qualification Status | Not Qualified | |
Seated Height-Max | 2 mm | |
Settling Time-Nom (tstl) | 0.2 µs | |
Supply Voltage-Nom | 5 V | |
Surface Mount | YES | |
Technology | BICMOS | |
Temperature Grade | OTHER | |
Terminal Form | GULL WING | |
Terminal Pitch | 1.27 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Width | 5.3 mm |
Alternate Parts for PCM1702U
This table gives cross-reference parts and alternative options found for PCM1702U. The Form Fit Function (FFF) tab will give you the options that are more likely to serve as direct pin-to-pin alternates or drop-in parts. The Functional Equivalents tab will give you options that are likely to match the same function of PCM1702U, but it may not fit your design. Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.
Part Number | Manufacturer | Composite Price | Description | Compare |
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PCM1702U-KE6 | Texas Instruments | Check for Price | 120dB SNR Stereo DAC with BiCMOS Advanced Sign Magnitude Architecture 20-SO | PCM1702U vs PCM1702U-KE6 |
PCM1702U Frequently Asked Questions (FAQ)
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The recommended power-on sequence is to apply VCC first, followed by VREF, and then the analog and digital inputs. This ensures proper device operation and prevents damage.
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The analog input filter should be designed to reject noise and aliasing. A 3rd-order Butterworth filter with a cutoff frequency of 40 kHz is recommended. The filter should also provide a gain of 1-2 dB to optimize the signal-to-noise ratio.
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The recommended clock frequency is 256 fs (where fs is the sampling frequency). The clock jitter tolerance is ±50 ppm, and the clock amplitude should be between 2.5 V and 5 V.
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The PCM1702U outputs 24-bit data in MSB-first, two's complement format. The data is output on the D0-D23 pins, with D0 being the MSB. The output data rate is equal to the sampling frequency.
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The PCM1702U requires a solid ground plane and separate analog and digital ground planes. The analog and digital supplies should be decoupled with 10 μF and 100 nF capacitors, respectively. The layout should also minimize noise coupling between analog and digital signals.