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IC FPGA SOC
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
M2S090TS-1FGG484T2 by Microsemi Corporation is a Field Programmable Gate Array.
Field Programmable Gate Arrays are under the broader part category of Programmable Logic Devices.
Programmable Logic Devices (PLDs) are reconfigurable digital components that can be customized for different applications, offering flexibility and improved performance over fixed logic devices. Read more about Programmable Logic Devices on our Programmable Logic part category page.
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M2S090TS-1FGG484T2
Microsemi Corporation
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Datasheet
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M2S090TS-1FGG484T2
Microsemi Corporation
IC FPGA SOC
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Pbfree Code | Yes | |
Rohs Code | Yes | |
Part Life Cycle Code | Transferred | |
Ihs Manufacturer | MICROSEMI CORP | |
Reach Compliance Code | compliant | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Microsemi Corporation | |
JESD-609 Code | e1 | |
Operating Temperature-Max | 125 °C | |
Operating Temperature-Min | -40 °C | |
Peak Reflow Temperature (Cel) | 250 | |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
Supply Voltage-Max | 1.26 V | |
Supply Voltage-Min | 1.14 V | |
Supply Voltage-Nom | 1.2 V | |
Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) | |
Time@Peak Reflow Temperature-Max (s) | 40 |
This table gives cross-reference parts and alternative options found for M2S090TS-1FGG484T2. The Form Fit Function (FFF) tab will give you the options that are more likely to serve as direct pin-to-pin alternates or drop-in parts. The Functional Equivalents tab will give you options that are likely to match the same function of M2S090TS-1FGG484T2, but it may not fit your design. Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.
Part Number | Manufacturer | Composite Price | Description | Compare |
---|---|---|---|---|
M2S090TS-1FGG484 | Microsemi Corporation | Check for Price | Field Programmable Gate Array, 86316-Cell, CMOS, PBGA484, FBGA-484 | M2S090TS-1FGG484T2 vs M2S090TS-1FGG484 |
M2S090TS-1FG484 | Microsemi Corporation | Check for Price | Field Programmable Gate Array, 86316-Cell, CMOS, PBGA484, FBGA-484 | M2S090TS-1FGG484T2 vs M2S090TS-1FG484 |
M2S090TS-1FG676I | Microsemi Corporation | Check for Price | Field Programmable Gate Array, 86316-Cell, CMOS, PBGA676, FBGA-676 | M2S090TS-1FGG484T2 vs M2S090TS-1FG676I |
M2S090TS-1FGG676 | Microsemi Corporation | Check for Price | Field Programmable Gate Array, 86316-Cell, CMOS, PBGA676, FBGA-676 | M2S090TS-1FGG484T2 vs M2S090TS-1FGG676 |
M2S090TS-1FGG676I | Microsemi Corporation | Check for Price | Field Programmable Gate Array, PBGA676, FBGA-676 | M2S090TS-1FGG484T2 vs M2S090TS-1FGG676I |
M2S090TS-1FGG676T2 | Microsemi Corporation | Check for Price | IC FPGA SOC | M2S090TS-1FGG484T2 vs M2S090TS-1FGG676T2 |
M2S090TS-1FG484I | Microsemi Corporation | Check for Price | Field Programmable Gate Array, 86316-Cell, CMOS, PBGA484, FBGA-484 | M2S090TS-1FGG484T2 vs M2S090TS-1FG484I |
Microsemi provides a PCB design guide and layout recommendations in their documentation, including the 'M2S090TS-1FGG484T2 FPGA PCB Design Guide' and 'Microsemi FPGA PCB Design and Layout Guidelines'. These resources provide guidance on signal integrity, power distribution, and thermal management.
Microsemi recommends using an external POR circuit, such as the MIC5239 or MIC5255, which can provide a clean and reliable power-on reset signal to the FPGA. The datasheet provides guidelines for POR circuit design and implementation.
The M2S090TS-1FGG484T2 FPGA has a maximum junction temperature (TJ) of 100°C. To ensure reliable operation, it's essential to implement proper thermal management, including heat sinks, thermal interfaces, and airflow management. Microsemi provides thermal management guidelines in their documentation, including the 'M2S090TS-1FGG484T2 FPGA Thermal Management Guide'.
Microsemi provides detailed documentation on clock management in their 'M2S090TS-1FGG484T2 FPGA Clock Management User Guide'. This guide covers PLL configuration, clock distribution, and clock domain crossing (CDC) techniques.
Microsemi provides guidelines for high-speed signal integrity in their 'M2S090TS-1FGG484T2 FPGA High-Speed Transceiver User Guide'. This guide covers topics such as transmission line design, signal termination, and jitter budgeting.