Part Details for M2S090T-1FCSG325I by Microchip Technology Inc
Results Overview of M2S090T-1FCSG325I by Microchip Technology Inc
- Distributor Offerings: (10 listings)
- Number of FFF Equivalents: (0 replacements)
- CAD Models: (Request Part)
- Number of Functional Equivalents: (0 options)
- Part Data Attributes: (Available)
- Reference Designs: (Not Available)
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M2S090T-1FCSG325I Information
M2S090T-1FCSG325I by Microchip Technology Inc is a Field Programmable Gate Array.
Field Programmable Gate Arrays are under the broader part category of Programmable Logic Devices.
Programmable Logic Devices (PLDs) are reconfigurable digital components that can be customized for different applications, offering flexibility and improved performance over fixed logic devices. Read more about Programmable Logic Devices on our Programmable Logic part category page.
Price & Stock for M2S090T-1FCSG325I
| Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
33AJ8553
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Newark | Smartfusion2 Soc Fpga, Arm Cortex-M3, 86Kles 325 Tfbga 11X13.5X1.16Mm Tray Rohs Compliant: Yes |Microchip M2S090T-1FCSG325I RoHS: Compliant Min Qty: 176 Package Multiple: 1 Date Code: 0 Container: Bulk | 0 |
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$205.1600 / $217.0500 | Buy Now |
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DISTI #
M2S090T-1FCSG325I-ND
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DigiKey | IC SOC CORTEX-M3 166MHZ 325BGA Min Qty: 176 Lead time: 14 Weeks Container: Tray | Temporarily Out of Stock |
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$217.0502 | Buy Now |
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DISTI #
M2S090T-1FCSG325I
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Avnet Americas | SMARTFUSION2 - Trays (Alt: M2S090T-1FCSG325I) RoHS: Compliant Min Qty: 176 Package Multiple: 176 Lead time: 14 Weeks, 0 Days Container: Tray | 0 |
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$175.2194 / $187.2000 | Buy Now |
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DISTI #
494-M2S090T1FCSG325I
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Mouser Electronics | SoC FPGA SmartFusion2 SoC FPGA, ARM Cortex-M3, 86KLEs RoHS: Compliant | 0 |
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$217.0500 | Order Now |
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DISTI #
M2S090T-1FCSG325I
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Microchip Technology Inc | SmartFusion2 SoC FPGA, ARM Cortex-M3, 86KLEs, TFBGA, Projected EOL: 2049-02-04 COO: South Korea ECCN: EAR99 RoHS: Compliant Lead time: 14 Weeks, 0 Days Container: Tray |
0 Alternates Available |
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$104.7400 / $220.2400 | Buy Now |
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Onlinecomponents.com | RoHS: Compliant | 0 |
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$189.8200 / $557.1100 | Buy Now |
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NAC | M2S090T-1FCSG325I RoHS: Compliant Min Qty: 176 Package Multiple: 176 Container: Tray | 0 |
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$182.6300 / $213.9400 | Buy Now |
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DISTI #
M2S090T-1FCSG325I
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Avnet Silica | SMARTFUSION2 (Alt: M2S090T-1FCSG325I) RoHS: Compliant Min Qty: 176 Package Multiple: 176 Lead time: 16 Weeks, 0 Days | Silica - 0 |
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Buy Now | |
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DISTI #
M2S090T-1FCSG325I
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EBV Elektronik | SMARTFUSION2 (Alt: M2S090T-1FCSG325I) RoHS: Compliant Min Qty: 176 Package Multiple: 176 Lead time: 15 Weeks, 0 Days | EBV - 0 |
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Buy Now | |
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Master Electronics | RoHS: Compliant | 0 |
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$189.8200 / $557.1100 | Buy Now |
Part Details for M2S090T-1FCSG325I
M2S090T-1FCSG325I CAD Models
M2S090T-1FCSG325I Part Data Attributes
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M2S090T-1FCSG325I
Microchip Technology Inc
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Datasheet
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M2S090T-1FCSG325I
Microchip Technology Inc
Field Programmable Gate Array, 86316-Cell, CMOS, PBGA325
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| Rohs Code | Yes | |
| Part Life Cycle Code | Active | |
| Ihs Manufacturer | MICROCHIP TECHNOLOGY INC | |
| Package Description | FCBGA-325 | |
| Reach Compliance Code | compliant | |
| HTS Code | 8542.31.00.01 | |
| Factory Lead Time | 14 Weeks | |
| JESD-30 Code | R-PBGA-B325 | |
| Length | 13.5 mm | |
| Moisture Sensitivity Level | 3 | |
| Number of Inputs | 180 | |
| Number of Logic Cells | 86184 | |
| Number of Outputs | 180 | |
| Number of Terminals | 325 | |
| Operating Temperature-Max | 100 °C | |
| Operating Temperature-Min | -40 °C | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | TFBGA | |
| Package Equivalence Code | BGA325,21X21,20 | |
| Package Shape | RECTANGULAR | |
| Package Style | GRID ARRAY, THIN PROFILE, FINE PITCH | |
| Peak Reflow Temperature (Cel) | 250 | |
| Programmable Logic Type | FPGA SOC | |
| Seated Height-Max | 1.16 mm | |
| Supply Voltage-Max | 1.26 V | |
| Supply Voltage-Min | 1.14 V | |
| Supply Voltage-Nom | 1.2 V | |
| Surface Mount | YES | |
| Terminal Finish | TIN SILVER COPPER | |
| Terminal Form | BALL | |
| Terminal Pitch | 0.5 mm | |
| Terminal Position | BOTTOM | |
| Time@Peak Reflow Temperature-Max (s) | 40 | |
| Width | 11 mm |
M2S090T-1FCSG325I Frequently Asked Questions (FAQ)
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A 4-layer PCB with a solid ground plane and thermal vias is recommended for optimal thermal performance. The device should be placed near a thermal pad or heat sink to dissipate heat efficiently.
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A POR circuit can be implemented using an external resistor and capacitor connected to the POR pin. The recommended values are R = 1 kΩ and C = 10 μF. This ensures a reliable reset signal during power-up.
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The maximum allowed clock skew between the FPGA and external memory is 1.5 ns. This ensures reliable data transfer and minimizes the risk of data corruption.
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To optimize power consumption, use the FPGA's built-in power management features, such as clock gating and dynamic voltage and frequency scaling. Additionally, optimize the design to minimize switching activity and use low-power modes when possible.
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The recommended method for configuring the FPGA's PLLs is to use the Microchip's Libero SoC design software, which provides a graphical interface for configuring the PLLs and generating the necessary configuration files.