Part Details for LMP2012WG-QMLV by National Semiconductor Corporation
Results Overview of LMP2012WG-QMLV by National Semiconductor Corporation
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LMP2012WG-QMLV Information
LMP2012WG-QMLV by National Semiconductor Corporation is an Operational Amplifier.
Operational Amplifiers are under the broader part category of Amplifier Circuits.
Amplifier circuits use external power to increase the amplitude of an input signal. They can be used to perform linear amplifications or logarithmic functions. Read more about Amplifier Circuits on our Amplifier Circuits part category page.
Part Details for LMP2012WG-QMLV
LMP2012WG-QMLV CAD Models
LMP2012WG-QMLV Part Data Attributes
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LMP2012WG-QMLV
National Semiconductor Corporation
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LMP2012WG-QMLV
National Semiconductor Corporation
IC DUAL OP-AMP, 60 uV OFFSET-MAX, 3 MHz BAND WIDTH, CDSO10, CERAMIC, SOIC-10, Operational Amplifier
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| Rohs Code | No | |
| Part Life Cycle Code | Transferred | |
| Ihs Manufacturer | NATIONAL SEMICONDUCTOR CORP | |
| Part Package Code | SOIC | |
| Package Description | CERAMIC, SOIC-10 | |
| Pin Count | 10 | |
| Reach Compliance Code | not_compliant | |
| ECCN Code | EAR99 | |
| HTS Code | 8542.33.00.01 | |
| Amplifier Type | OPERATIONAL AMPLIFIER | |
| Architecture | VOLTAGE-FEEDBACK | |
| Average Bias Current-Max (IIB) | 0.000003 µA | |
| Common-mode Reject Ratio-Nom | 130 dB | |
| Frequency Compensation | YES | |
| Input Offset Voltage-Max | 60 µV | |
| JESD-30 Code | R-CDSO-G10 | |
| JESD-609 Code | e0 | |
| Low-Bias | YES | |
| Low-Offset | YES | |
| Micropower | NO | |
| Moisture Sensitivity Level | 1 | |
| Number of Functions | 2 | |
| Number of Terminals | 10 | |
| Operating Temperature-Max | 125 °C | |
| Operating Temperature-Min | -55 °C | |
| Package Body Material | CERAMIC, METAL-SEALED COFIRED | |
| Package Code | SOP | |
| Package Equivalence Code | SOP10,.4 | |
| Package Shape | RECTANGULAR | |
| Package Style | SMALL OUTLINE | |
| Peak Reflow Temperature (Cel) | 260 | |
| Power | NO | |
| Programmable Power | NO | |
| Qualification Status | Not Qualified | |
| Screening Level | 38535V;38534K;883S | |
| Seated Height-Max | 2.042 mm | |
| Slew Rate-Nom | 4 V/us | |
| Supply Current-Max | 3.5 mA | |
| Supply Voltage Limit-Max | 5.8 V | |
| Supply Voltage-Nom (Vsup) | 5 V | |
| Surface Mount | YES | |
| Technology | CMOS | |
| Temperature Grade | MILITARY | |
| Terminal Finish | Tin/Lead (Sn63Pb37) | |
| Terminal Form | GULL WING | |
| Terminal Pitch | 1.27 mm | |
| Terminal Position | DUAL | |
| Time@Peak Reflow Temperature-Max (s) | 40 | |
| Unity Gain BW-Nom | 3000 | |
| Voltage Gain-Min | 17780 | |
| Wideband | NO | |
| Width | 6.12 mm |
LMP2012WG-QMLV Frequently Asked Questions (FAQ)
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National Semiconductor recommends a thermal pad on the bottom of the package, connected to a large copper area on the PCB to dissipate heat. A minimum of 2oz copper thickness is recommended, and the thermal pad should be connected to a ground plane to reduce thermal resistance.
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To ensure stability, National Semiconductor recommends following the datasheet's guidelines for gain and phase margin, and using a compensation capacitor if necessary. Additionally, the op-amp's output should be properly terminated, and the input should be properly biased and filtered to prevent oscillations.
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The maximum power dissipation for the LMP2012WG-QMLV is 1.4W, which is calculated based on the maximum junction temperature (150°C) and the thermal resistance of the package (45°C/W). Exceeding this limit can cause the op-amp to overheat and fail.
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The LMP2012WG-QMLV is rated for operation up to 125°C, but National Semiconductor recommends derating the power dissipation at higher temperatures to prevent overheating. The op-amp's performance may also degrade at higher temperatures, so careful testing and characterization are recommended.
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The LMP2012WG-QMLV has built-in ESD protection, but National Semiconductor recommends following proper handling and assembly procedures to prevent ESD damage. Additionally, the op-amp's inputs and outputs should be properly terminated and filtered to prevent ESD events from damaging the device.