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Field Programmable Gate Array,
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
LFE5UM-45F-7BG381I by Lattice Semiconductor Corporation is a Field Programmable Gate Array.
Field Programmable Gate Arrays are under the broader part category of Programmable Logic Devices.
Programmable Logic Devices (PLDs) are reconfigurable digital components that can be customized for different applications, offering flexibility and improved performance over fixed logic devices. Read more about Programmable Logic Devices on our Programmable Logic part category page.
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
55AJ1630
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Newark | Lattice Ecp5 , 43.8K Luts, 1.1V, Serdes Rohs Compliant: Yes |Lattice Semiconductor LFE5UM-45F-7BG381I RoHS: Compliant Min Qty: 90 Package Multiple: 1 Date Code: 0 Container: Bulk | 0 |
|
$52.0200 / $54.7000 | Buy Now |
DISTI #
220-1997-ND
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DigiKey | IC FPGA 203 I/O 381CABGA Min Qty: 1 Lead time: 16 Weeks Container: Tray |
231 In Stock |
|
$47.8125 / $59.3000 | Buy Now |
DISTI #
842-LFE5UM45F7BG381I
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Mouser Electronics | FPGA - Field Programmable Gate Array ECP5 FPGA 45K LUTs w/ SERDES RoHS: Compliant | 852 |
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$49.7300 / $59.3000 | Buy Now |
DISTI #
85914898
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Verical | FPGA LatticeECP5 Family 44000 Cells 40nm Technology 1.1V 381-Pin CABGA Tray RoHS: Compliant Min Qty: 90 Package Multiple: 90 Date Code: 2433 | Americas - 20700 |
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$45.2000 / $46.6700 | Buy Now |
DISTI #
SMC-LFE5UM-45F-7BG381I
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Sensible Micro Corporation | OEM Excess 5-7 Days Leadtime, We are an AS6081 Certified Vendor, 1 Yr Warranty RoHS: Not Compliant Min Qty: 25 Lead time: 2 Weeks, 0 Days | 65 |
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RFQ | |
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Flip Electronics | Stock | 3000 |
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RFQ | |
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Vyrian | Programmable ICs | 5849 |
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RFQ |
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LFE5UM-45F-7BG381I
Lattice Semiconductor Corporation
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Datasheet
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LFE5UM-45F-7BG381I
Lattice Semiconductor Corporation
Field Programmable Gate Array,
|
Rohs Code | Yes | |
Part Life Cycle Code | Active | |
Ihs Manufacturer | LATTICE SEMICONDUCTOR CORP | |
Package Description | CABGA-381 | |
Reach Compliance Code | compliant | |
ECCN Code | 3A991.D | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Lattice Semiconductor | |
Clock Frequency-Max | 164 MHz | |
JESD-30 Code | S-PBGA-B381 | |
Length | 17 mm | |
Moisture Sensitivity Level | 3 | |
Number of CLBs | 5500 | |
Number of Inputs | 203 | |
Number of Logic Cells | 44000 | |
Number of Outputs | 203 | |
Number of Terminals | 381 | |
Operating Temperature-Max | 100 °C | |
Operating Temperature-Min | -40 °C | |
Organization | 5500 CLBS | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | FBGA | |
Package Equivalence Code | BGA381,20X20,32 | |
Package Shape | SQUARE | |
Package Style | GRID ARRAY, FINE PITCH | |
Peak Reflow Temperature (Cel) | 260 | |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
Seated Height-Max | 1.76 mm | |
Supply Voltage-Max | 1.155 V | |
Supply Voltage-Min | 1.045 V | |
Supply Voltage-Nom | 1.1 V | |
Surface Mount | YES | |
Terminal Form | BALL | |
Terminal Pitch | 0.8 mm | |
Terminal Position | BOTTOM | |
Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | |
Width | 17 mm |
The LFE5UM-45F-7BG381I has an operating temperature range of -40°C to 100°C.
Lattice recommends using a CDC IP core or a synchronizer FIFO to implement clock domain crossing in the LFE5UM-45F-7BG381I. The IP core or FIFO should be configured according to the specific clock domain requirements.
The power consumption of the LFE5UM-45F-7BG381I depends on the specific design and usage. However, the typical static power consumption is around 100-200 mW, and the dynamic power consumption is around 100-500 mW, depending on the clock frequency and toggle rate.
Yes, the LFE5UM-45F-7BG381I is capable of supporting high-speed interfaces like PCIe and SATA. However, the specific implementation and IP cores used will depend on the specific requirements and standards.
To optimize the design for power consumption and area usage, use the Lattice Diamond design software to implement power-saving techniques like clock gating, voltage scaling, and resource sharing. Additionally, use the FPGA's built-in power management features and optimize the design for area usage by using the available resources efficiently.