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Field Programmable Gate Array, PBGA121, CSFBGA-121
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
LCMXO3LF-1300E-5MG121I by Lattice Semiconductor Corporation is a Field Programmable Gate Array.
Field Programmable Gate Arrays are under the broader part category of Programmable Logic Devices.
Programmable Logic Devices (PLDs) are reconfigurable digital components that can be customized for different applications, offering flexibility and improved performance over fixed logic devices. Read more about Programmable Logic Devices on our Programmable Logic part category page.
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
55AJ0620
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Newark | Lattice Machxo3Lf , 1280 Luts, 1.2V Rohs Compliant: Yes |Lattice Semiconductor LCMXO3LF-1300E-5MG121I RoHS: Compliant Min Qty: 490 Package Multiple: 1 Date Code: 0 Container: Bulk | 0 |
|
$8.2300 / $8.4700 | Buy Now |
DISTI #
LCMXO3LF-1300E-5MG121I-ND
|
DigiKey | IC FPGA 100 I/O 121CSFBGA Min Qty: 1 Lead time: 16 Weeks Container: Tray |
310 In Stock |
|
$7.5625 / $9.4500 | Buy Now |
DISTI #
842-O3LF1300E5MG121I
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Mouser Electronics | FPGA - Field Programmable Gate Array Lattice MachXO3LF , 1280 LUTs, 1.2V RoHS: Compliant | 9580 |
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$7.5600 / $9.1600 | Buy Now |
DISTI #
V36:1790_13794212
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Arrow Electronics | FPGA MACHXO3 Family 1300 Cells 40nm Technology 1.2V Automotive 121-Pin CSFBGA Tray RoHS: Compliant Min Qty: 1 Package Multiple: 1 Lead time: 16 Weeks Date Code: 2435 | Americas - 490 |
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$7.2300 / $8.3150 | Buy Now |
DISTI #
84739283
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Verical | FPGA MACHXO3 Family 1300 Cells 40nm Technology 1.2V Automotive 121-Pin CSFBGA Tray RoHS: Compliant Min Qty: 1 Package Multiple: 1 Date Code: 2435 | Americas - 490 |
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$7.2720 / $8.6990 | Buy Now |
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Bristol Electronics | 8 |
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RFQ |
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LCMXO3LF-1300E-5MG121I
Lattice Semiconductor Corporation
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Datasheet
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LCMXO3LF-1300E-5MG121I
Lattice Semiconductor Corporation
Field Programmable Gate Array, PBGA121, CSFBGA-121
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Rohs Code | Yes | |
Part Life Cycle Code | Active | |
Ihs Manufacturer | LATTICE SEMICONDUCTOR CORP | |
Package Description | CSFBGA-121 | |
Reach Compliance Code | compliant | |
ECCN Code | EAR99 | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Lattice Semiconductor | |
Clock Frequency-Max | 127.2 MHz | |
JESD-30 Code | S-PBGA-B121 | |
JESD-609 Code | e1 | |
Length | 6 mm | |
Moisture Sensitivity Level | 3 | |
Number of CLBs | 160 | |
Number of Inputs | 100 | |
Number of Logic Cells | 1300 | |
Number of Outputs | 100 | |
Number of Terminals | 121 | |
Operating Temperature-Max | 100 °C | |
Operating Temperature-Min | -40 °C | |
Organization | 160 CLBS | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | VFBGA | |
Package Equivalence Code | BGA121,11X11,20 | |
Package Shape | SQUARE | |
Package Style | GRID ARRAY, VERY THIN PROFILE, FINE PITCH | |
Peak Reflow Temperature (Cel) | 260 | |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
Seated Height-Max | 1 mm | |
Supply Voltage-Max | 1.26 V | |
Supply Voltage-Min | 1.14 V | |
Supply Voltage-Nom | 1.2 V | |
Surface Mount | YES | |
Terminal Finish | TIN SILVER COPPER | |
Terminal Form | BALL | |
Terminal Pitch | 0.5 mm | |
Terminal Position | BOTTOM | |
Width | 6 mm |
Lattice provides a PCB layout guide and reference design files for the LCMXO3LF-1300E-5MG121I. It's recommended to follow these guidelines to ensure optimal signal integrity and minimize signal degradation.
Lattice recommends using a power management IC (PMIC) specifically designed for FPGAs, such as the Lattice Power Manager. This ensures proper power sequencing, voltage regulation, and monitoring for the FPGA.
The LCMXO3LF-1300E-5MG121I has a thermal design power (TDP) of 1.5W. Ensure good airflow, use a heat sink if necessary, and follow Lattice's thermal management guidelines to prevent overheating and ensure reliable operation.
Lattice provides a range of security features, including bitstream encryption, authentication, and secure boot mechanisms. Implement these features to protect your IP and prevent unauthorized access to the FPGA's configuration.
Lattice recommends using the Lattice Diamond software development environment, which provides a comprehensive design flow, including synthesis, place-and-route, and verification tools.