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Part Details for CD4042BF3A by Texas Instruments
Results Overview of CD4042BF3A by Texas Instruments
- Distributor Offerings: (4 listings)
- Number of FFF Equivalents: (0 replacements)
- CAD Models: (Available)
- Number of Functional Equivalents: (0 options)
- Part Data Attributes: (Available)
- Reference Designs: (Not Available)
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
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CD4042BF3A Information
CD4042BF3A by Texas Instruments is an FF/Latch.
FF/Latches are under the broader part category of Logic Components.
Digital logic governs the behavior of signals in electronic circuits, enabling complex decisions based on simple binary inputs (yes/no). Logic components perform operations from these signals. Read more about Logic Components on our Logic part category page.
Available Datasheets
| Part # | Manufacturer | Description | Datasheet |
|---|---|---|---|
| CD4042BF3A | Texas Instruments | CMOS Quad Clocked ''D'' Latch 16-CDIP -55 to 125 |
Price & Stock for CD4042BF3A
| Part # | Distributor | Description | Stock | Price | Buy | |
|---|---|---|---|---|---|---|
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DISTI #
296-CD4042BF3A-ND
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DigiKey | IC D-TYPE TRANSP 4:4 16-CDIP Lead time: 12 Weeks Container: Tube | Temporarily Out of Stock |
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Buy Now | |
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DISTI #
J56:1989_00548053
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Arrow Electronics | Latch Transparent 4-CH D-Type 16-Pin CDIP Tube RoHS: Not Compliant Min Qty: 25 Package Multiple: 25 Lead time: 18 Weeks Date Code: 2229 | Europe - 50 |
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$15.2950 / $18.8140 | Buy Now |
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Quest Components | 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16 | 1 |
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$11.8744 | Buy Now |
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New Advantage Corporation | RoHS: Compliant Min Qty: 1 Package Multiple: 1 | 712 |
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$9.1000 / $12.2500 | Buy Now |
Part Details for CD4042BF3A
CD4042BF3A CAD Models
CD4042BF3A Part Data Attributes
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CD4042BF3A
Texas Instruments
Buy Now
Datasheet
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CD4042BF3A
Texas Instruments
CMOS Quad Clocked ''D'' Latch 16-CDIP -55 to 125
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| Pbfree Code | Yes | |
| Rohs Code | No | |
| Part Life Cycle Code | Active | |
| Ihs Manufacturer | TEXAS INSTRUMENTS INC | |
| Part Package Code | DIP | |
| Pin Count | 16 | |
| Reach Compliance Code | not_compliant | |
| ECCN Code | EAR99 | |
| HTS Code | 8542.39.00.01 | |
| Samacsys Manufacturer | Texas Instruments | |
| Additional Feature | PROGRAMMABLE TRIGGER TYPE | |
| Family | 4000/14000/40000 | |
| JESD-30 Code | R-GDIP-T16 | |
| JESD-609 Code | e0 | |
| Length | 19.56 mm | |
| Load Capacitance (CL) | 50 pF | |
| Logic IC Type | D LATCH | |
| Max I(ol) | 0.0024 A | |
| Number of Bits | 4 | |
| Number of Functions | 4 | |
| Number of Terminals | 16 | |
| Operating Temperature-Max | 125 °C | |
| Operating Temperature-Min | -55 °C | |
| Output Polarity | COMPLEMENTARY | |
| Package Body Material | CERAMIC, GLASS-SEALED | |
| Package Code | DIP | |
| Package Equivalence Code | DIP16,.3 | |
| Package Shape | RECTANGULAR | |
| Package Style | IN-LINE | |
| Packing Method | TUBE | |
| Power Supply Current-Max (ICC) | 0.6 mA | |
| Prop. Delay@Nom-Sup | 200 ns | |
| Propagation Delay (tpd) | 500 ns | |
| Qualification Status | Not Qualified | |
| Schmitt Trigger | NO | |
| Screening Level | 38535Q/M;38534H;883B | |
| Seated Height-Max | 5.08 mm | |
| Supply Voltage-Max (Vsup) | 18 V | |
| Supply Voltage-Min (Vsup) | 3 V | |
| Supply Voltage-Nom (Vsup) | 5 V | |
| Surface Mount | NO | |
| Technology | CMOS | |
| Temperature Grade | MILITARY | |
| Terminal Finish | Tin/Lead (Sn/Pb) | |
| Terminal Form | THROUGH-HOLE | |
| Terminal Pitch | 2.54 mm | |
| Terminal Position | DUAL | |
| Trigger Type | NEGATIVE EDGE | |
| Width | 7.62 mm | |
| fmax-Min | 8 MHz |
CD4042BF3A Frequently Asked Questions (FAQ)
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The recommended operating voltage range for CD4042BF3A is 3V to 18V, although it can operate from 2V to 20V with reduced performance.
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To ensure proper power-on and power-off, connect a 0.1uF to 1uF capacitor between VCC and GND, and a 1kΩ to 10kΩ pull-up resistor between VCC and the enable pin (if used).
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The CD4042BF3A can handle clock frequencies up to 10MHz, but the maximum frequency may vary depending on the specific application and operating conditions.
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To implement a reset function, connect the reset pin (R) to VCC through a 1kΩ to 10kΩ resistor, and then connect the reset pin to GND through a 0.1uF to 1uF capacitor. This will ensure a clean reset signal.
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The enable pin (E) is used to enable or disable the clock signal. When the enable pin is high, the clock signal is enabled, and when it's low, the clock signal is disabled.