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Dual Positive-Edge-Triggered D-Type Flip-Flops 14-TSSOP -40 to 125
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
SN74LV74APWRG4 by Texas Instruments is an FF/Latch.
FF/Latches are under the broader part category of Logic Components.
Digital logic governs the behavior of signals in electronic circuits, enabling complex decisions based on simple binary inputs (yes/no). Logic components perform operations from these signals. Read more about Logic Components on our Logic part category page.
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
595-SN74LV74APWRG4
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Mouser Electronics | Flip Flops Dual Pos-Edge-Trgrd D-Type Flip-Flop ALT 595-SN74LV74APWR RoHS: Compliant | 1988 |
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$0.2180 / $1.1600 | Buy Now |
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Vyrian | Logic ICs | 3049 |
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RFQ | |
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Win Source Electronics | Dual Positive-Edge-Triggered D-Type Flip-Flops | 143090 |
|
$0.1964 / $0.2945 | Buy Now |
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SN74LV74APWRG4
Texas Instruments
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Datasheet
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SN74LV74APWRG4
Texas Instruments
Dual Positive-Edge-Triggered D-Type Flip-Flops 14-TSSOP -40 to 125
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Pbfree Code | Yes | |
Rohs Code | Yes | |
Part Life Cycle Code | Active | |
Ihs Manufacturer | TEXAS INSTRUMENTS INC | |
Part Package Code | TSSOP | |
Pin Count | 14 | |
Reach Compliance Code | compliant | |
ECCN Code | EAR99 | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Texas Instruments | |
Family | LV/LV-A/LVX/H | |
JESD-30 Code | R-PDSO-G14 | |
JESD-609 Code | e4 | |
Length | 5 mm | |
Load Capacitance (CL) | 50 pF | |
Logic IC Type | D FLIP-FLOP | |
Max Frequency@Nom-Sup | 45000000 Hz | |
Max I(ol) | 0.012 A | |
Moisture Sensitivity Level | 1 | |
Number of Bits | 1 | |
Number of Functions | 2 | |
Number of Terminals | 14 | |
Operating Temperature-Max | 125 °C | |
Operating Temperature-Min | -40 °C | |
Output Polarity | COMPLEMENTARY | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | TSSOP | |
Package Equivalence Code | TSSOP14,.25 | |
Package Shape | RECTANGULAR | |
Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | |
Packing Method | TR | |
Peak Reflow Temperature (Cel) | 260 | |
Power Supply Current-Max (ICC) | 0.02 mA | |
Prop. Delay@Nom-Sup | 17.5 ns | |
Propagation Delay (tpd) | 23 ns | |
Qualification Status | Not Qualified | |
Seated Height-Max | 1.2 mm | |
Supply Voltage-Max (Vsup) | 5.5 V | |
Supply Voltage-Min (Vsup) | 2 V | |
Supply Voltage-Nom (Vsup) | 2.5 V | |
Surface Mount | YES | |
Technology | CMOS | |
Temperature Grade | AUTOMOTIVE | |
Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) | |
Terminal Form | GULL WING | |
Terminal Pitch | 0.65 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Trigger Type | POSITIVE EDGE | |
Width | 4.4 mm | |
fmax-Min | 110 MHz |
This table gives cross-reference parts and alternative options found for SN74LV74APWRG4. The Form Fit Function (FFF) tab will give you the options that are more likely to serve as direct pin-to-pin alternates or drop-in parts. The Functional Equivalents tab will give you options that are likely to match the same function of SN74LV74APWRG4, but it may not fit your design. Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.
Part Number | Manufacturer | Composite Price | Description | Compare |
---|---|---|---|---|
74LV74PW-T | NXP Semiconductors | Check for Price | IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, TSSOP1-14, FF/Latch | SN74LV74APWRG4 vs 74LV74PW-T |
MC74LVX74DT | Motorola Mobility LLC | Check for Price | LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, TSSOP-14 | SN74LV74APWRG4 vs MC74LVX74DT |
74LV74PW | NXP Semiconductors | Check for Price | IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, TSSOP1-14, FF/Latch | SN74LV74APWRG4 vs 74LV74PW |
74LV74PW,112 | NXP Semiconductors | Check for Price | 74LV74 - Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP 14-Pin | SN74LV74APWRG4 vs 74LV74PW,112 |
74LV74PW,112 | Nexperia | Check for Price | 74LV74 - Dual D-type flip-flop with set and reset; positive-edge trigger@en-us TSSOP 14-Pin | SN74LV74APWRG4 vs 74LV74PW,112 |
SN74LV74APWRE4 | Texas Instruments | Check for Price | Dual Positive-Edge-Triggered D-Type Flip-Flops 14-TSSOP -40 to 125 | SN74LV74APWRG4 vs SN74LV74APWRE4 |
N74LV74PW-T | NXP Semiconductors | Check for Price | IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, FF/Latch | SN74LV74APWRG4 vs N74LV74PW-T |
935175140112 | NXP Semiconductors | Check for Price | IC LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP1-16, FF/Latch | SN74LV74APWRG4 vs 935175140112 |
The maximum clock frequency of the SN74LV74APWRG4 is 100 MHz.
To ensure proper initialization, connect the preset (PRE) and clear (CLR) inputs to VCC or GND, and use a pull-up or pull-down resistor to prevent floating inputs.
The recommended operating voltage range for the SN74LV74APWRG4 is 2.7V to 3.6V.
No, the SN74LV74APWRG4 is not 5V tolerant. It is designed to operate at 3.3V or lower voltage levels.
To reduce power consumption, use a lower clock frequency, reduce the input transition times, and minimize the number of output transitions.