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105dB SNR Stereo USB2.0 FS DAC with line-out (Self-powered) 28-SSOP
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
PCM2702E/2K by Texas Instruments is a Digital to Analog Converter.
Digital to Analog Converters are under the broader part category of Converters.
A converter is an electrical circuit that transforms electric energy into a different form that will support a elecrical load needed by a device. Read more about Converters on our Converters part category page.
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
86021111
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Verical | DAC 2-CH Delta-Sigma 16-bit 28-Pin SSOP T/R RoHS: Compliant Min Qty: 29 Package Multiple: 1 Date Code: 1001 | Americas - 23800 |
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$10.3875 / $12.9875 | Buy Now |
DISTI #
86008366
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Verical | DAC 2-CH Delta-Sigma 16-bit 28-Pin SSOP T/R RoHS: Compliant Min Qty: 29 Package Multiple: 1 | Americas - 1500 |
|
$10.3875 / $12.9875 | Buy Now |
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Rochester Electronics | D/A Converter, 1 Func, Serial Input Loading, 12us Settling Time, PDSO28 RoHS: Compliant Status: Obsolete Min Qty: 1 | 25300 |
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$8.3100 / $10.3900 | Buy Now |
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PCM2702E/2K
Texas Instruments
Buy Now
Datasheet
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Compare Parts:
PCM2702E/2K
Texas Instruments
105dB SNR Stereo USB2.0 FS DAC with line-out (Self-powered) 28-SSOP
|
Pbfree Code | No | |
Rohs Code | Yes | |
Part Life Cycle Code | Obsolete | |
Ihs Manufacturer | TEXAS INSTRUMENTS INC | |
Part Package Code | SSOP | |
Package Description | GREEN, PLASTIC, SSOP-28 | |
Pin Count | 28 | |
Reach Compliance Code | compliant | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Texas Instruments | |
Analog Output Voltage-Max | 3.41 V | |
Analog Output Voltage-Min | ||
Converter Type | D/A CONVERTER | |
Input Bit Code | BINARY | |
Input Format | SERIAL | |
JESD-30 Code | R-PDSO-G28 | |
JESD-609 Code | e4 | |
Length | 10.2 mm | |
Moisture Sensitivity Level | 1 | |
Number of Bits | 16 | |
Number of Functions | 1 | |
Number of Terminals | 28 | |
Operating Temperature-Max | 70 °C | |
Operating Temperature-Min | ||
Package Body Material | PLASTIC/EPOXY | |
Package Code | SSOP | |
Package Equivalence Code | SSOP28,.3 | |
Package Shape | RECTANGULAR | |
Package Style | SMALL OUTLINE, SHRINK PITCH | |
Peak Reflow Temperature (Cel) | 260 | |
Qualification Status | Not Qualified | |
Seated Height-Max | 2 mm | |
Settling Time-Nom (tstl) | 12 µs | |
Supply Voltage-Nom | 5 V | |
Surface Mount | YES | |
Temperature Grade | COMMERCIAL | |
Terminal Finish | NICKEL PALLADIUM GOLD | |
Terminal Form | GULL WING | |
Terminal Pitch | 0.65 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Width | 5.3 mm |
This table gives cross-reference parts and alternative options found for PCM2702E/2K. The Form Fit Function (FFF) tab will give you the options that are more likely to serve as direct pin-to-pin alternates or drop-in parts. The Functional Equivalents tab will give you options that are likely to match the same function of PCM2702E/2K, but it may not fit your design. Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.
Part Number | Manufacturer | Composite Price | Description | Compare |
---|---|---|---|---|
PCM2702E/2KG4 | Texas Instruments | Check for Price | SERIAL INPUT LOADING, 12us SETTLING TIME, 16-BIT DAC, PDSO28, GREEN, PLASTIC, SSOP-28 | PCM2702E/2K vs PCM2702E/2KG4 |
The recommended power-up sequence is to apply VCC first, followed by VDD, and then the clock signal. This ensures that the internal voltage regulators are properly initialized.
To configure the PCM2702E/2K for master mode operation, set the MCLK pin as the clock source, and connect the BCLK and WCLK pins to the external clock source. Also, set the MS bit in the control register to '1' to enable master mode.
The maximum allowed capacitance on the VCC and VDD pins is 10uF. Exceeding this value may cause power-up issues or affect the device's performance.
During power-down, the digital output pins (e.g., I2S, SPDIF) should be tri-stated to prevent back-powering the device. This can be achieved by setting the output enable pins (e.g., OEN) to '0' or by using an external buffer with a tri-state output.
Keep analog and digital signals separate, and use a star-configuration for the analog signals to minimize noise coupling. Also, use a solid ground plane and avoid routing digital signals under the analog signals.