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74HC74; 74HCT74 - Dual D-type flip-flop with set and reset; positive edge-trigger@en-us SSOP1 14-Pin
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
74HCT74DB,112 by Nexperia is an FF/Latch.
FF/Latches are under the broader part category of Logic Components.
Digital logic governs the behavior of signals in electronic circuits, enabling complex decisions based on simple binary inputs (yes/no). Logic components perform operations from these signals. Read more about Logic Components on our Logic part category page.
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
2156-74HCT74DB,112-1727-ND
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DigiKey | IC FF D-TYPE DOUBLE 1BIT 14SSOP Min Qty: 1388 Lead time: 1 Weeks Container: Bulk MARKETPLACE PRODUCT |
14510 In Stock |
|
$0.2200 | Buy Now |
DISTI #
2156-74HCT74DB,112-954-ND
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DigiKey | IC FF D-TYPE DOUBLE 1BIT 14SSOP Min Qty: 1388 Lead time: 1 Weeks Container: Bulk MARKETPLACE PRODUCT |
12548 In Stock |
|
$0.2200 | Buy Now |
DISTI #
86087736
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Verical | Flip Flop D-Type Pos-Edge 2-Element 14-Pin SSOP Bulk RoHS: Compliant Min Qty: 1739 Package Multiple: 1 Date Code: 1801 | Americas - 7644 |
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$0.1611 / $0.2158 | Buy Now |
DISTI #
86088723
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Verical | Flip Flop D-Type Pos-Edge 2-Element 14-Pin SSOP Bulk RoHS: Compliant Min Qty: 1739 Package Multiple: 1 Date Code: 1701 | Americas - 6866 |
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$0.1611 / $0.2158 | Buy Now |
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Rochester Electronics | D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, SSOP14 RoHS: Compliant Status: Obsolete Min Qty: 1 | 14510 |
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$0.1289 / $0.2079 | Buy Now |
DISTI #
74HCT74DB.112
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TME | IC: digital, D flip-flop, Ch: 2, CMOS,TTL, SMD, SSOP14, tube, HCT Min Qty: 3 | 377 |
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$0.1410 / $0.1900 | Buy Now |
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74HCT74DB,112
Nexperia
Buy Now
Datasheet
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Compare Parts:
74HCT74DB,112
Nexperia
74HC74; 74HCT74 - Dual D-type flip-flop with set and reset; positive edge-trigger@en-us SSOP1 14-Pin
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Rohs Code | Yes | |
Part Life Cycle Code | Obsolete | |
Ihs Manufacturer | NEXPERIA | |
Part Package Code | SSOP1 | |
Package Description | SSOP-14 | |
Pin Count | 14 | |
Manufacturer Package Code | SOT337-1 | |
Reach Compliance Code | compliant | |
HTS Code | 8542.39.00.01 | |
Factory Lead Time | 4 Weeks | |
Date Of Intro | 2017-02-01 | |
Samacsys Manufacturer | Nexperia | |
Family | HCT | |
JESD-30 Code | R-PDSO-G14 | |
JESD-609 Code | e4 | |
Length | 6.2 mm | |
Logic IC Type | D FLIP-FLOP | |
Moisture Sensitivity Level | 1 | |
Number of Bits | 1 | |
Number of Functions | 2 | |
Number of Terminals | 14 | |
Operating Temperature-Max | 125 °C | |
Operating Temperature-Min | -40 °C | |
Output Polarity | COMPLEMENTARY | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | SSOP | |
Package Shape | RECTANGULAR | |
Package Style | SMALL OUTLINE, SHRINK PITCH | |
Peak Reflow Temperature (Cel) | 260 | |
Propagation Delay (tpd) | 53 ns | |
Seated Height-Max | 2 mm | |
Supply Voltage-Max (Vsup) | 5.5 V | |
Supply Voltage-Min (Vsup) | 4.5 V | |
Supply Voltage-Nom (Vsup) | 5 V | |
Surface Mount | YES | |
Technology | CMOS | |
Temperature Grade | AUTOMOTIVE | |
Terminal Finish | NICKEL PALLADIUM GOLD | |
Terminal Form | GULL WING | |
Terminal Pitch | 0.65 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Trigger Type | POSITIVE EDGE | |
Width | 5.3 mm | |
fmax-Min | 18 MHz |
This table gives cross-reference parts and alternative options found for 74HCT74DB,112. The Form Fit Function (FFF) tab will give you the options that are more likely to serve as direct pin-to-pin alternates or drop-in parts. The Functional Equivalents tab will give you options that are likely to match the same function of 74HCT74DB,112, but it may not fit your design. Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.
Part Number | Manufacturer | Composite Price | Description | Compare |
---|---|---|---|---|
SN74HCT74DBR | Texas Instruments | $0.1366 | Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SSOP -40 to 85 | 74HCT74DB,112 vs SN74HCT74DBR |
935175180118 | NXP Semiconductors | Check for Price | IC HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 5.30 MM, PLASTIC, MO-150AB, SOT-337-1, SSOP-14, FF/Latch | 74HCT74DB,112 vs 935175180118 |
935175180112 | Nexperia | Check for Price | D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14 | 74HCT74DB,112 vs 935175180112 |
74HCT74DB,118 | NXP Semiconductors | Check for Price | 74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger SSOP1 14-Pin | 74HCT74DB,112 vs 74HCT74DB,118 |
74HCT74DB,112 | NXP Semiconductors | Check for Price | 74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger SSOP1 14-Pin | 74HCT74DB,112 vs 74HCT74DB,112 |
74HCT74DB | NXP Semiconductors | Check for Price | IC HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 5.30 MM, PLASTIC, MO-150, SOT-337-1, SSOP-14, FF/Latch | 74HCT74DB,112 vs 74HCT74DB |
74HCT74DB | Nexperia | Check for Price | D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14 | 74HCT74DB,112 vs 74HCT74DB |
The recommended operating voltage range for the 74HCT74DB,112 is 4.5V to 5.5V, with a typical voltage of 5V.
To ensure the flip-flop is properly reset during power-up, connect the reset pin (MR) to VCC through a pull-up resistor (e.g., 1kΩ) and add a capacitor (e.g., 100nF) from the reset pin to GND to filter out any noise.
The maximum clock frequency that the 74HCT74DB,112 can handle is 30MHz, but this may vary depending on the specific application and operating conditions.
While the 74HCT74DB,112 is specified for 5V operation, it can be used in a 3.3V system, but the output voltage levels may not be fully compliant with the HCT (High-Speed CMOS) standard. Additionally, the device's performance and noise immunity may be affected.
The asynchronous reset input (MR) should be connected to a logic high (VCC) during normal operation and only pulled low to reset the flip-flop. Ensure that the reset signal is synchronized with the clock signal to avoid metastability issues.